1. Field of the Invention
This invention relates to a semiconductor integrated circuit device such as a static random access memory (hereinafter called "SRAM") having a plurality of memory cells, each including of a flip-flop for data storage.
2. Description of Related Art
In a conventional SRAM, a memory cell array is arranged in a matrix configuration on a chip, and each memory cell is accessed by using one word-line and a pair of bit-lines selected on the basis of a decoded address signal. In the case of a complementary metal oxide semiconductor field-effect transistor (CMOS) SRAM, each memory cell typically contains as a storage circuit a flip-flop, composed of a pair of p-channel metal oxide semiconductor field effect transistors (PMOS transistors) and a pair of n-channel metal oxide semiconductor field effect transistors (NMOS transistors), and a further pair of NMOS transistors functioning as transfer gates. In each memory cell, the NMOS transistors of the transfer gates, connect the flip-flop storage circuit with the corresponding bit-lines, and are controlled by connection of their gates to the respective corresponding word-lines.
One end of each bit-line is connected to a power supply voltage line which provides a supply voltage Vcc, through an NMOS transistor as a load. The other end of each bit-line is connected to a corresponding one of a pair of data-lines, through a respective NMOS transistor functioning as a transfer gate. Each such pair of transfer gates for a pair of the bit-lines, is controlled by the same column signal, to be turned on and off.
The data on some bit-line pairs require amplification and for the purpose the bit-lines are connected to a sense amplifier. Each pair of bit-lines is also connected, through a pair of data-lines, to a write driver, for writing data to each memory cell.
In such a device, the sense amplifier is activated by a control signal CN. The control signal CN is produced in response to a write enable signal WE.sub.N (active low) and a chip select signal CS.about. (active low). The sense amplifier amplifies a voltage difference between the data-lines.
The write driver is activated in response to an inverted control signal CN.sub.N. The signal CN.sub.N is obtained from an inverter that receives the control signal CN. The write driver delivers data to the data-lines on a pair of write data-lines.
During a read cycle of the device (also referred herein as a "read operation"), the control signal CN goes to a high level HIGH as selected between the binary logic levels, thereby turning the sense amplifier on (active). The write driver is not activated since the inverted control signal CN.sub.N is LOW. During a write cycle of the device (also referred to herein as a "write operation"), in turn, the control signal CN goes to the low level (LOW) of the binary logic levels, thereby turning the sense amplifier off (inactive), whereas the write driver is activated according to the inverted control signal CN.sub.N.
In such a conventional SRAM, the sense amplifier is turned on and off only by the control signal CN. The control signal maintains the same level throughout the entire read cycle, that is as long as the write enable signal WE.sub.N (active low) is HIGH (indicating the read cycle) and the chip select signal CS.about. (active low) is LOW (indicating the chip is selected). Therefore, the sense amplifier is continuously activated during the read cycle, even while the output enable signal OE.about. (active low) is HIGH, indicating that the output of the chip is disabled and in a floating state. (The output enable signal OE.about. is well known in circuits of this type). Such maintenance of the sense amplifier in an active state, while the chip output is disabled, is wasteful of power consumption.
During an initial portion of the read cycle, immediately after the write cycle, pairs of the data-lines and the bit-lines retain large voltage differences as a result of the write cycle. When the voltage on a word-line or a column-line shifts, to close a corresponding transfer gate, malfunctions in writing to the memory cell may occur, because the capacitance of the memory cell is much less than that of the bit-lines or the dam-lines, and such memory cell capacitance is thereby easily charged or discharged due to the large voltage differences at which those line and memory cell capacitances are coupled with each other. Therefore, to protect memory cells from such malfunctions in the conventional SRAM, the read operation is delayed for a predetermined "write recovery" time period, immediately after the data is written. This write recovery time period, however, prevents the SRAM from operating at a high speed.